R0 contains the instruction to disassemble, for the current system. R1 contains the address from which to assume the instruction came, which is needed for instructions such as B, BL, LDR Rn, [PC...], and so on. On exit, R1 points to a buffer which contains a zero terminated string. This string consists of the instruction mnemonic, and any operands, in the format used by the instruction. The length in R2 excludes the zero-byte. There may be comments following the operands, indicated by a semicolon, for example ; Undefined behaviour.

Earlier versions of the reference manuals defined this to be a 32bit value, assuming it to be for ARM. The SWI is now defined to disassemble an instruction in the current architecture of the system. This allows the SWI to be used on any system to decode instructions within the current system.

R0 contains the instruction to disassemble, for the current system. R1 contains the address from which to assume the instruction came, which is needed for instructions such as B, BL, LDR Rn, [PC...], and so on. On exit, R1 points to a buffer which contains a zero terminated string. This string consists of the instruction mnemonic, and any operands, in the format used by the instruction. The length in R2 excludes the zero-byte. There may be comments following the operands, indicated by a semicolon, for example ; Undefined behaviour.

Debugger_Flags changes the default format that the disasssembly uses for instructions, operands and comments. The flags control individual features of the disassembly. Flags are architecture specific. The flags will be modified by applying the BIC mask to clear bits, and then the EOR mask to invert flags.

The flags may also be controlled from the command line with , which uses the names of the flags to control their state.

For the ARM architecture, the flags may take the following values:

Use FD with R13, eg. STMDB R13 becomes STMFD R13. Use APCS-R register set and recognise C function entry. Use stack notation with LFM and SFM where possible. Use LFS and SFS in preference to LFM & SFM. Put quotes around SWI names. Use DCD instead of 'Undefined instruction', and BRK where DCD &x6000010 would be used. Use VDU x instead of SWI OS_WriteI+x. Use DCD instead of ANDEQ, MOV Rn,Rn (same register) etc. Use ADRL/ADRX instead of ADR then ADD/SUB on same reg. Use ADRW instead of ADD/SUB Rn,R12,#m and LDRW, STRW, LDRBW, STRBW instead of xxxx Rn,[R12,#m]. Append L to UMUL, UMLA, SMUL, SMLA (thus using the 'official' forms). Use LDRL instead of ADD/SUB Rn,Rm,#o + LDR Rn,[Rn,#p] and ADD/SUB Rm,Ra,#o + LDR Rn,[Ra,#p]! and STR instead of equivalent STRs. (The LDRWL form is enabled by this *and* UseADRW) Use NOP instead of MOV R0,R0. Use the old PSR suffixes _ctl, _flg, _all. Disassemble for wide display. Use HS and LO instead of CS and CC. Use x&lsl;y comments where possible for numbers ≥ 8192. This affects arithmetic and logic instructions. y is restricted to multiples of 4 if possible, unless x=1. Force all register names to lower case.

Display non-standard constant (x ROR y) as #x,y. This flag affects certain instructions in which the constant is not stored in the standard way, possibly having unexpected effects if you try to reassemble the code.
Affects: ANDS, ORRS, EORS, BICS, TEQ, TST (CMP and CMN are also affected). 16 encoded as 64&lsr;2 will be displayed as '#64,2'.

Debugger_DisassemblePlus takes the same parameters as , but overrides the default disassembly flags with explicit flags to use for this call. See for details of the flags.

This SWI is used to disassemble instructions in an architecture agnostic manner. Whilst can disassemble the current architecture, it does not provide the ability to decode in a thread safe manner, and does not support variable length instruction sequences. This SWI supports both these features, and allows greater control over the disassembly with flags.

The architecture identifier supplied is the same as that used by the module format, and OS_PlatformFeatures 64 interface.

To support variable length instructions, R1 contains the pointer to an instruction sequence to disassemble, and R2 contains the number of bytes which are available at the pointer. If insufficient bytes have been supplied, an error will be returned and R2 will be the negative number of bytes required.

If R5 is 0, or the value supplied is less than the size required for disassembly, an buffer overflow error (&hex;1E4) will be returned with R5 set to the negative size required. If R4 is set to 0 an internal buffer will be used (R5 must be set to a non-0 value).

The disassembly format will use a semi-colon to delimit any additional commentary, as in standard ARM disassembly format.